I'm Lokesh Siddhu

External Links: Google scholar, DBLP

Thermal Aware Runtime Management of 3D Architecture

3D integration enables higher performance, lower power, and compact form factors. However, it poses significant thermal challenges due to increased power density. Our work designs thermal-aware data and task mapping strategies to mitigate these issues.

Watch a 4-minute intro of this research.

Selected Publication(s):

1. Lokesh Siddhu, Rajesh Kedia, and Preeti Ranjan Panda. "CoreMemDTM: Integrated Processor Core and 3D Memory dynamic Thermal Management for Improved Performance.," DATE, 2022.
2. Shailja Pandey, Lokesh Siddhu, and Preeti Ranjan Panda. "NeuroCool: Dynamic Thermal Management of 3D DRAM for Deep Neural Networks through Customized Prefetching.," ACM TODAES, 2023.
3. Lokesh Siddhu, Rajesh Kedia, and Preeti Ranjan Panda. "Leakage-Aware Dynamic Thermal Management of 3D Memories.," ACM TODAES, 2020.
4. Lokesh Siddhu, and Preeti Ranjan Panda. "PredictNcool: Leakage Aware Thermal Management for 3D Memories Using a Lightweight Temperature Predictor.," ACM TECS, 2019. (Presented at ESWEEK/CODES+ISSS)

Toolchain:

CoMeT is an open-source simulation toolchain for thermal and performance modeling of 2D/2.5D/3D systems. Link to Repository

Systems with Non-Volatile Memories

Conventional memories like DRAM and SRAM are fast but volatile—data is lost on power-off. Non-volatile storage (e.g., Flash, HDD) retains data but is much slower. Emerging non-volatile memory (NVM) technologies combine the best of both: near-DRAM speeds, higher density, and data retention without power. However, NVMs face challenges such as limited write endurance and slower writes. Our research explores low-overhead techniques to address these. Some NVMs support multiple write modes—fast, medium, and slow—each with different trade-offs between latency, energy, and retention time (faster writes offer lower retention). We utilize this by assigning fast writes to short-lived data (e.g., intermediate variables), improving performance while managing retention. Designing efficient systems with NVM remains a key focus of our research.

Selected Publication(s):

1. Lokesh Siddhu, Hassan Nassar, Lars Bauer, Christian Hakert, Nils Hölscher, Jian-Jia Chen, and Jörg Henkel. "Swift-CNN: Leveraging PCM Memory’s Fast Write Mode to Accelerate CNNs.," IEEE ESL, 2023.
2. Jörg Henkel, Lokesh Siddhu, Lars Bauer, Jürgen Teich, Stefan Wildermann, Mehdi Tahoori, Mahta Mayahinia, Jeronimo Castrillon, Asif Ali Khan, Hamid Farzaneh, João Paulo C. de Lima, Jian-Jia Chen, Christian Hakert, Kuan-Hsun Chen, Chia-Lin Yang, and Hsiang-Yun Cheng. "Non-Volatile Memories: Challenges and Opportunities for Embedded System Architectures with Focus on Machine Learning Applications.," CASES, 2023.

Technical Service

Regular reviewer for ASP-DAC, ACM-CSUR, CODES+ISSS, DAC, DATE, ESL, ISLPED, IPDPS, TC, TCAD, TODAES, TPDS, TSIPI, TVLSI, VDAT, VLSID.

Awarded DAC 2024 Outstanding TPC Member.

Open Positions

We welcome applications for research staff, Ph.D. students, and M.Tech. positions.

Our work spans system-level research at the intersection of hardware and software. A strong foundation in computer architecture and digital logic is needed. Familiarity with Linux-based systems is also helpful.

If you're interested in exploring research opportunities, feel free to reach out via email.